The present invention relates to a semiconductor device that prevents electrostatic breakdown of a metal oxide semiconductor (MOS) transistor within a semiconductor integrated circuit.
Countermeasures against breakdown due to static electricity are important for protecting the high reliability of the semiconductor integrated circuits. On the other hand, it has become practically difficult to achieve this countermeasure against breakdown due to static electricity because of miniaturization and complexity of semiconductor integrated circuits in recent years.
Particularly, generally, the semiconductor integrated circuits include MOS transistors. The input of a CMOS (complementary metal oxide semiconductor) transistor includes a high-impedance electrode and another electrode separated by a thin high-insulation film covering the insulated electrode. A capacitor is disadvantageously formed between these electrodes of the transistor which may be sometimes electrically charged. If this capacitor is electrically charged, it may momentarily output a high voltage via an electrode pad connected to the transistor.
Similarly, switching operation of mechanical switches or semiconductor switches provided outside of the semiconductor integrated circuit may cause a high voltage to be momentarily applied to the electrode pad connected to the transistor.
When such momentarily generated high voltage is applied to transistors or other external elements as described above, what is called a surge breakdown is generated, like breakdown of these transistors, and a reduction in their life. To avoid this problem, usually a surge protection circuit is disposed between the transistor and the electrode pad of this transistor.
FIG. 5 is a circuit diagram of NMOS (N-channel metal oxide semiconductor) transistor circuit as an example of semiconductor devices. This transistor circuit 100 includes NMOS transistor MN10 and surge protection circuit 101. The NMOS transistor MN10 has its drain (source) connected to the electrode pad 102, and has its source (drain) and back gate connected to the ground. The surge protection circuit 101 is connected in parallel with the NMOS transistor MN10 as concerned to the electrode pad 102. Further, the surge protection circuit 101 includes two diodes connected in series. Cathode of one of these diodes is connected to a power source terminal, and anode of the other diode is connected to the ground. Node of these diodes is connected to the electrode pad 102.
FIG. 6 is a cross-sectional construction diagram for explaining the operation of the NMOS transistor shown in FIG. 5. Consider that surge voltage is applied to the electrode pad 102. As a result, surge current flows into the surge protection circuit 101, and therefore the NMOS transistor MN10 is not destroyed. Thus, surge breakdown of this transistor is prevented.
However, as shown in FIG. 6, when the input impedance of the NMOS transistor MN10 at the electrode pad 102 becomes lower than the input impedance of the surge protection circuit 101 due to the connection of a back gate P+ diffusion layer of the NMOS transistor MN10 to ground, the surge current pierces a junction between a drain (source) N diffusion layer 112 and a Pxe2x88x92 well 113. The surge current then passes through a back gate P+ diffusion layer 111 and a Pxe2x88x92 substrate 114 to reach the ground. This brings about electrostatic breakdown of the junction surface.
In order to prevent the electrostatic breakdown, conventionally, a transistor of bigger size is used thereby increasing the backward withstand voltage between the drain (source) N diffusion layer 112 and the Pxe2x88x92 well 113.
However, there is a problem that, along with the reduction in the sizes of transistors based on reduction in the chip size and the refining of the processes following this trend, the drain (source) diffusion layer has become thinner. As a result, it has become difficult to obtain a sufficient surge withstand voltage.
It is an object of this invention to provide a semiconductor device capable of preventing the electrostatic breakdown even when the semiconductor device is composed of sufficiently fine MOS transistors.
The semiconductor device according to one aspect of this invention includes a MOS transistor having a source or a drain connected with a wire to an electrode pad; a surge protection circuit connected in parallel with the wire that connects the MOS transistor and the electrode pad; and an impedance adding unit that has input impedance higher than input impedance of the surge protection circuit and that is connected to a back gate of the MOS transistor.
According to the above-mentioned aspect, in a MOS transistor circuit having a surge protection circuit connected in parallel with a MOS transistor, the impedance adding unit is provided at the back gate of the MOS transistor. Therefore, it is possible to apply an input impedance higher than an input impedance of the surge protection circuit to between the back gate of this MOS transistor and the ground (or the power source terminal).
The semiconductor device according to another aspect of this invention includes a plurality of MOS transistors and same number of electrode pads as the MOS transistors, wherein each of the MOS transistor having a source or a drain connected with a wire to corresponding the electrode pad; same number of surge protection circuits as the MOS transistors, wherein each of the surge protection circuit being connected in parallel with the wire that connects corresponding the MOS transistor and the electrode pad; and an impedance adding unit that has input impedance higher than input impedance of each of the surge protection circuit and that is connected in common to back gates of the MOS transistors.
According to the above-mentioned aspect, in a plurality of MOS transistor circuits having a surge protection circuit connected in parallel with each MOS transistor, the impedance adding unit connected in common to the back gate of each MOS transistor is provided. Therefore, one impedance adding unit can apply an input impedance higher than an input impedance of the surge protection circuit to between the back gate of each MOS transistor and the ground (or the power source terminal).
The semiconductor device according to still another aspect of this invention includes a MOS transistor having a source or a drain connected with a wire to an electrode pad; and a surge protection circuit connected in parallel with the wire that connects the MOS transistor and the electrode pad, wherein back gate of the MOS transistor is connected to a point of a semiconductor circuit at which point the impedance is higher than input impedance of the surge protection circuit.
According to the above-mentioned aspect, in a MOS transistor circuit having a surge protection circuit connected in parallel with a MOS transistor, a high impedance point of other semiconductor circuit is connected to a back gate of the MOS transistor. Therefore, it is possible to apply an input impedance higher than an input impedance of the surge protection circuit to between the back gate of this MOS transistor and the ground (or the power source terminal).